Integrated Peripherals
- Analog
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- Analog-to-Digital Converter
- The MSP430 line offers two types of Analog-to-Digital Conversion (ADC). 10- and 12-bit Successive Approximation converters, as well as a 16-bit Sigma-Delta converter. Data transfer controllers and a 16 word conversion-and-control buffer allow the MSP430 to convert and store samples without CPU intervention, minimizing power consumption.
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- Analog Pool
- The Analog Pool (A-POOL) module can be configured as an ADC, DAC, Comparator, SVS or temperature sensor. It allows flexibility for the user to program a series of analog functions with only one setup.
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- Comparator A, A+
- The MSP430's comparator module provides precision slope Analog-to-Digital Conversions. Monitors external analog signals and provides voltage and resistor value measurement. Capable of selectable power modes.
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- DAC12
- The DAC12 module is a 12-bit, voltage-output DAC featuring internal/external reference selection and programmable settling time for optimal power consumption. It can be configured in 8- or 12-bit mode. When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.
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- Op Amps
- Feature single supply, low current operation with rail-to-rail outputs and programmable settling times. Software selectable configuration options: unity gain mode, comparator mode, inverting PGA, non-inverting PGA, differential and instrumentation amplifier.
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- Sigma Delta (SD)
- The SD16/SD16_A/SD24_A modules each feature 16-/24-bit sigma-delta A/D converters with an internal 1.2-V reference. Each converter has up to eight fully differential multiplexed inputs, including a built-in temperature sensor. The converters are second-order oversampling sigma-delta modulators with selectable oversampling ratios of up to 1024 (SD16_A/SD24_A) or 256 (SD16).
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- Timers
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- Basic Timer (BT)
- The BT has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The BT is extended to provide an integrated RTC. An internal calendar compensates for months with less than 31 days and includes leap-year correction.
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- Real-Time Clock
- RTC_A/B are 32-bit hardware counter modules that provide clock counters with a calendar, a flexible programmable alarm, and calibration. The RTC_B includes a switchable battery backup system that provides the ability for the RTC to operate when the primary supply fails.
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- 16-bit Timers
- Timer_A, Timer_B and Timer_D are asynchronous 16-bit timers/counters with up to seven capture/compare registers and various operating modes. The timers support multiple capture/compares, PWM outputs, and interval timing. They also have extensive interrupt capabilities. Timer_B introduces additional features such as programmable timer lengths (8, 10, 12 or 16-bit), while Timer_D introduces a high-resolution mode (4ns resolution).
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- Watchdog (WDT+)
- The WDT+ performs a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
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- System
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- Advanced Encryption Standard (AES)
- The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to the advanced encryption standard in hardware, and can be configured with user software.
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- Brown-Out Reset (BOR)
- The BOR circuit detects low supply voltages and resets the device by triggering a power-on reset (POR) signal when power is applied or removed. The MSP430 MCU’s zero-power BOR circuit is continuously turned on, including in all low-power modes.
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- Direct Memory Access (DMA) Controller
- The DMA controller transfers data from one address to another across the entire address range without CPU intervention. The DMA increases the throughput of peripheral modules and reduces system power consumption. The module features up to three independent transfer channels.
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- Although the MSP430's DMA subsystem is very capable it has several flaws, the most significant of which is the lack of an external transfer strobe. Although a DMA transfer can be triggered externally, there is no external indication of completion of a transfer. Consequently DMA to and from external sources is limited to external trigger per byte transfers, rather than full blocks automatically via DMA. This can lead to significant complexity (as in requiring extensive hand tweaking of code) when implementing processor to processor or processor to USB communications.[2] The reference cited uses an obscure timer mode to generate high speed strobes for DMA transfers. Unfortunately, the timers are not flexible enough to easily make up for the lack of an external DMA transfer strobe.
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- DMA operations that involve word transfers to byte locations cause truncation to 8 bits rather than conversion to two byte transfers. This makes DMA with A/D or D/A 16 bit values less useful than it could be (although it is possible to DMA these values through port A or B on some versions of the MSP 430 using an externally visible trigger per transfer such as a timer output).
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- Enhanced Emulation Module (EEM)
- The EEM provides different levels of debug features such as 2-8 hardware breakpoints, complex breakpoints, break when read/write occurs at specified address, and more. Embedded into all flash-based MSP430 devices.
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- Hardware multiplier
- Some MSP430 models include a memory-mapped hardware multiplier peripheral which performs various 16×16+32→33-bit multiply-accumulate operations. Unusually for the MSP430, this peripheral does include an implicit 2-bit write-only register, which makes it effectively impossible to context switch. This peripheral does not interfere with CPU activities and can be accessed by the DMA. The MPY on all MSP430F5xx and some MSP430F4xx devices feature up to 32-bit x 32-bit.
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- The 8 registers used are:
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Address Name Function 0x130 MPY Operand1 for unsigned multiply 0x132 MPYS Operand1 for signed multiply 0x134 MAC Operand1 for unsigned multiply-accumulate 0x136 MACS Operand1 for signed multiply-accumulate 0x138 OP2 Second operand for multiply operation 0x13A ResLo Low word of multiply result 0x13C ResHi High word of multiply result 0x13E SumExt Carry out of multiply-accumulate
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- The first operand is written to one of four 16-bit registers. The address written determines the operation performed. While the value written can be read back from any of the registers, the register number written to cannot be recovered.
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- If a multiply-accumulate operation is desired, the
ResLoandResHiregisters must also be initialized.
- If a multiply-accumulate operation is desired, the
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- Then, each time a write is performed to the
OP2register, a multiply is performed and the result stored or added to the result registers. TheSumExtregister is a read-only register that contains the carry out of the addition (0 or 1) in case of an unsigned multiply), or the sign extension of the 32-bit sum (0 or -1) in case of a signed multiply. In the case of a signed multiply-accumulate, theSumExtvalue must be combined with the most significant bit of the priorSumHicontents to determine the true carry out result (-1, 0, or +1).
- Then, each time a write is performed to the
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- The result is available after three clock cycles of delay, which is the time required to fetch a following instruction and a following index word. Thus, the delay is typically invisible. An explicit delay is only required if using an indirect addressing mode to fetch the result.
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- Memory Protection Unit (MPU)
- The FRAM MPU protects against accidental writes to designated read-only memory segments or execution of code from a constant memory. The MPU can set any portioning of memory with bit level addressing, making the complete memory accessible for read, write and execute operations in FRAM devices.
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- Power Management Module (PMM)
- The PMM generates a supply voltage for the core logic, and provides several mechanisms for the supervision and monitoring of both the voltage applied to the device and the voltage generated for the core. It is integrated with a low-dropout voltage regulator (LDO), brown-out reset (BOR), and a supply voltage supervisor and monitor.
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- Supply-Voltage Supervisor (SVS)
- The SVS is a configurable module used to monitor the AVCC supply voltage or an external voltage. The SVS can be configured to set a flag or generate a power-on reset (POR) when the supply voltage or external voltage drops below a user-selected threshold.
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- Communication and Interface
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- Capacitive Touch Sense I/Os
- The integrated capacitive touch sense I/O module offers several benefits to touch button and touch slider applications. The system does not require external components to create the self-oscillation (reducing bill of materials) and the capacitor (that defines the frequency of the self-oscillation) can be connected directly. In addition, there is no need for external MUXes to allow multiple pads and each I/O pad can directly serve as a cap sense input. A hysteresis of ~0.7V ensures robust operation. Control and sequencing is done completely in software.
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- General Purpose I/Os
- MSP430 devices have up to 12 digital I/O ports implemented. Each port has eight I/O pins. Every I/O pin can be configured as either input or output, and can be individually read or written to. Ports P1 and P2 have interrupt capability. MSP430F2xx, F5xx and some F4xx devices feature built-in, individually configurable pull-up or pull-down resistors.
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- Sub-GHZ RF Front End
- The flexible CC1101 sub-1GHz transceiver delivers the sensitivity and blocking performance required to achieve successful communication links in any RF environment. It also features low current consumption and supports flexible data rates and modulation formats.
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- USART (UART, SPI, I²C)
- The universal synchronous/asychrnous receive/transmit (USART) peripheral interface supports asynchronous RS-232 and synchronous SPI communication with one hardware module. The MSP430F15x/16x USART modules also support I²C, programmable baud rate, and independent interrupt capability for receive and transmit.
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- USB
- The USB module is fully compliant with the USB 2.0 specification and supports control, interrupt and bulk transfers at a data rate of 12 Mbps (full speed). The module supports USB suspend, resume and remote wake-up operations and can be configured for up to eight input and eight output endpoints. The module includes an integrated physical interface (PHY); a phase-locked loop (PLL) for USB clock generation; and a flexible power-supply system enabling bus-powered and self-powered devices.
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- USCI (UART, SPI, I²C, LIN, IrDA)
- The universal serial communication interface (USCI) module features two independent channels that can be used simultaneously. The asynchronous channel (USCI_A) supports UART mode; SPI mode; pulse shaping for IrDA; and automatic baud-rate detection for LIN communications. The synchronous channel (USCI_B) supports I²C and SPI modes.
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- USI (SPI, I²C)
- The universal serial interface (USI) module is a synchronous serial communication interface with a data length of up to 16-bits and can support SPI and I²C communication with minimal software.
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- Metering
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- ESP430 (integrated in FE42xx devices)
- The ESP430CE module performs metering calculations independent of the CPU. Module has separate SD16, HW multiplier, and the ESP430 embedded processor engine for single-phase energy-metering applications.
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- Scan Interface (SIF)
- The SIF module, a programmable state machine with an analog front end, is used to automatically measure linear or rotational motion with the lowest possible power consumption. The module features support for different types of LC and resistive sensors and for quadrature encoding.
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- Display
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- LCD/LCD_A/LCD_B
- The LCD/LCD_A controller directly drives LCD displays for up to 196 segments. Supports static, 2-mux, 3-mux, and 4-mux LCDs. LCD_A module has integrated charge pump for contrast control. LCD_B enables blinking of individual segments with separate blinking memory.
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[edit]Software development environment
Texas Instruments provides various hardware experimenter boards that support large (approximately two centimeters square) and small (approximately one millimeter square) MSP430 chips. TI also provides software development tools, both directly, and in conjunction with partners (see the full list of compilers, assemblers, and IDEs). One such toolchain is the IAR C/C++ compiler andIntegrated development environment, or IDE. A Kickstart edition can be downloaded for free from TI or IAR; it is limited to 8 KB of C/C++ code in the compiler and debugger (assembly languageprograms of any size can be developed and debugged with this free toolchain).
TI also combines a version of its own compiler and tools with its Eclipse-based Code Composer Studio IDE ("CCS"). It sells full-featured versions, and offers a free version for download which has a code size limit of 16 KB. CCS supports in-circuit emulators, and includes a simulator and other tools; it can also work with other processors sold by TI.
The open source community produces a freely available software development toolset based on the GNU toolset. The GNU compiler is currently declined in three versions:
(MSPGCC)
There is a very early llvm-msp430 project, which may eventually provide better support for MSP430 in LLVM.
Other commercial development tool sets, which include editor, compiler, linker, assembler, debugger and in some cases code wizards, are available. VisSim, a block diagram language for model based development, generates efficient fixed point C-Code directly from the diagram.[3] VisSim generated code for a closed loop ADC+PWM based PID control on the F2013 compiles to less than 1 KB flash and 100 bytes RAM.[4] VisSim has on-chip peripheral blocks for the entire MSP430 family I²C, ADC, SD16, PWM.
[edit]Low cost development platforms
The MSP430F2013 and its siblings are set apart by the fact that (except for the MSP430G2 Value Line) it is the only MSP430 part that is available in a dual in-line package (DIP). Other variants in this family are only available in various surface-mount packages. TI has gone to some trouble to support the eZ430 development platform by making the raw chips easy for hobbyists to use in prototypes.
[edit]eZ430-F2013
TI has tackled the low-budget problem by offering a very small experimenter board, the eZ430-F2013, on a USB stick. This makes it easy for designers to choose the MSP430 chip for inexpensive development platforms that can be used with a computer. The eZ430-F2013 contains an MSP430F2013 microcontroller on a detachable prototyping board, and accompanying CD with development software. It is helpful for schools, hobbyists and garage inventors. It is also welcomed by engineers in large companies prototyping projects with capital budget problems.
[edit]MSP430 Launchpad
Texas Instruments released the MSP430 Launchpad in July 2010. The MSP430 Launchpad has an onboard flash emulator, USB, 2 programmable LEDs, and 1 programmable push button.[5]
[edit]
MSP430 CPU
The MSP430 CPU uses a von Neumann architecture, with a single address space for instructions and data. Memory is byte-addressed, and pairs of bytes are combined little-endian to make 16-bit words.
The processor contains 16 16-bit registers,[6] of which 4 are dedicated to special purposes: R0 is the program counter, R1 is the stack pointer, R2 is the status register, and R3 is a special register called the constant generator, providing access to 6 commonly used constant values without requiring an additional operand. R3 always reads as 0 and writes to it are ignored. R4 through R15 are available for general use.
The instruction set is very simple; there are 27 instructions in three families. Most instructions are available in .B (8-bit byte) and .W (16-bit word) suffixed versions, depending on the value of a B/W bit: the bit is set to 1 for 8-bit and 0 for 16-bit. A missing suffix is equivalent to .W. Byte operations to memory affect only the addressed byte, while byte operations to registers clear the most significant byte.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Instruction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 0 | opcode | B/W | As | register | Single-operand arithmetic | ||||||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | B/W | As | register | RRC Rotate right (1 bit) through carry | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | As | register | SWPB Swap bytes | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | B/W | As | register | RRA Rotate right (1 bit) arithmetic | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | As | register | SXT Sign extend byte to word | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | B/W | As | register | PUSH Push value onto stack | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | As | register | CALL Subroutine call; push PC and move source to PC | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | RETI Return from interrupt; pop SR then pop PC |
| 0 | 0 | 1 | condition | 10-bit signed offset | Conditional jump; PC = PC + 2×offset | |||||||||||
| 0 | 0 | 1 | 0 | 0 | 0 | 10-bit signed offset | JNE/JNZ Jump if not equal/zero | |||||||||
| 0 | 0 | 1 | 0 | 0 | 1 | 10-bit signed offset | JEQ/JZ Jump if equal/zero | |||||||||
| 0 | 0 | 1 | 0 | 1 | 0 | 10-bit signed offset | JNC/JLO Jump if no carry/lower | |||||||||
| 0 | 0 | 1 | 0 | 1 | 1 | 10-bit signed offset | JC/JHS Jump if carry/higher or same | |||||||||
| 0 | 0 | 1 | 1 | 0 | 0 | 10-bit signed offset | JN Jump if negative | |||||||||
| 0 | 0 | 1 | 1 | 0 | 1 | 10-bit signed offset | JGE Jump if greater or equal | |||||||||
| 0 | 0 | 1 | 1 | 1 | 0 | 10-bit signed offset | JL Jump if less | |||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | 10-bit signed offset | JMP Jump (unconditionally) | |||||||||
| opcode | source | Ad | B/W | As | destination | Two-operand arithmetic | ||||||||||
| 0 | 1 | 0 | 0 | source | Ad | B/W | As | destination | MOV Move source to destination | |||||||
| 0 | 1 | 0 | 1 | source | Ad | B/W | As | destination | ADD Add source to destination | |||||||
| 0 | 1 | 1 | 0 | source | Ad | B/W | As | destination | ADDC Add source and carry to destination | |||||||
| 0 | 1 | 1 | 1 | source | Ad | B/W | As | destination | SUBC Subtract source from destination (with carry) | |||||||
| 1 | 0 | 0 | 0 | source | Ad | B/W | As | destination | SUB Subtract source from destination | |||||||
| 1 | 0 | 0 | 1 | source | Ad | B/W | As | destination | CMP Compare (pretend to subtract) source from destination | |||||||
| 1 | 0 | 1 | 0 | source | Ad | B/W | As | destination | DADD Decimal add source to destination (with carry) | |||||||
| 1 | 0 | 1 | 1 | source | Ad | B/W | As | destination | BIT Test bits of source AND destination | |||||||
| 1 | 1 | 0 | 0 | source | Ad | B/W | As | destination | BIC Bit clear (dest &= ~src) | |||||||
| 1 | 1 | 0 | 1 | source | Ad | B/W | As | destination | BIS Bit set (logical OR) | |||||||
| 1 | 1 | 1 | 0 | source | Ad | B/W | As | destination | XOR Exclusive or source with destination | |||||||
| 1 | 1 | 1 | 1 | source | Ad | B/W | As | destination | AND Logical AND source with destination (dest &= src) | |||||||
Instructions are 16 bits, followed by up to two 16-bit extension words. Addressing modes are specified by the 2-bit As field and the 1-bit Ad field. Some special versions can be constructed using R0, and modes other than register direct using R2 (the status register) and R3 (the constant generator) are interpreted specially. Ad can use only a subset of the addressing modes for As.
Indexed addressing modes add a 16-bit extension word to the instruction. If both source and destination are indexed, the source extension word comes first. x refers to the next extension word in the instruction stream in the table below.
| As | Ad | Register | Syntax | Description |
|---|---|---|---|---|
| 00 | 0 | n | Rn | Register direct. The operand is the contents of Rn. |
| 01 | 1 | n | x(Rn) | Indexed. The operand is in memory at address Rn+x. |
| 10 | — | n | @Rn | Register indirect. The operand is in memory at the address held in Rn. |
| 11 | — | n | @Rn+ | Indirect autoincrement. As above, then the register is incremented by 1 or 2. |
| Addressing modes using R0 (PC) | ||||
| 01 | 1 | 0 (PC) | ADDR | Symbolic. Equivalent to x(PC). The operand is in memory at address PC+x. |
| 11 | — | 0 (PC) | #x | Immediate. Equivalent to @PC+. The operand is the next word in the instruction stream. |
| Addressing modes using R2 (SR) and R3 (CG), special-case decoding | ||||
| 01 | 1 | 2 (SR) | &ADDR | Absolute. The operand is in memory at address x. |
| 10 | — | 2 (SR) | #4 | Constant. The operand is the constant 4. |
| 11 | — | 2 (SR) | #8 | Constant. The operand is the constant 8. |
| 00 | — | 3 (CG) | #0 | Constant. The operand is the constant 0. |
| 01 | — | 3 (CG) | #1 | Constant. The operand is the constant 1. There is no index word. |
| 10 | — | 3 (CG) | #2 | Constant. The operand is the constant 2. |
| 11 | — | 3 (CG) | #−1 | Constant. The operand is the constant −1. |
Instructions generally take 1 cycle per word fetched or stored, so instruction times range from 1 cycle for a simple register-register instruction to 6 cycles for an instruction with both source and destination indexed.
The MSP430X extension with 20-bit addressing adds additional instructions that can require up to 10 clock cycles. Setting or clearing a peripheral bit takes two clocks. A jump, taken or not takes two clocks. With the 2xx series 2 MCLKs is 125 ns at 16 MHz.
Moves to the program counter are allowed and perform jumps. Return from subroutine, for example, is implemented as MOV @SP+,PC.
When R0 (PC) or R1 (SP) are used with the autoincrement addressing mode, they are always incremented by two. Other registers (R4 through R15) are incremented by the operand size, either 1 or 2 bytes.
The status register contains 4 arithmetic status bits, a global interrupt enable, and 4 bits that disable various clocks to enter low-power mode. When handling an interrupt, the processor saves the status register on the stack and clears the low-power bits. If the interrupt handler does not modify the saved status register, returning from the interrupt will then resume the original low-power mode.
[edit]Pseudo-operations
A number of additional instructions are implemented as aliases for forms of the above. For example, there is no specific "return from subroutine" instruction, but it is implemented as "MOV @SP+,PC". Emulated instructions are:
| Emulated | Actual | Description |
|---|---|---|
| ADC.x dst | ADDC.x #0,dst | Add carry to destination |
| BR dst | MOV dst,PC | Branch to destination |
| CLRC | BIC #1,SR | Clear carry bit |
| CLRN | BIC #4,SR | Clear negative bit |
| CLRZ | BIC #2,SR | Clear zero bit |
| DADC.x dst | DADD.x #0,dst | Decimal add carry to destination |
| DEC.x dst | SUB.x #1,dst | Decrement |
| DECD.x dst | SUB.x #2,dst | Double decrement |
| DINT | BIC #8,SR | Disable interrupts |
| EINT | BIS #8,SR | Enable interrupts |
| INC.x dst | ADD.x #1,dst | Increment |
| INCD.x dst | ADD.x #2,dst | Double increment |
| INV.x dst | XOR.x #−1,dst | Invert |
| NOP | MOV #0,R3 | No operation |
| POP dst | MOV @SP+,dst | Pop from stack |
| RET | MOV @SP+,PC | Return from subroutine |
| RLA.x dst | ADD.x dst,dst | Rotate left arithmetic (shift left 1 bit) |
| RLC.x dst | ADDC.x dst,dst | Rotate left through carry |
| SBC.x dst | SUBC.x #0,dst | Subtract borrow (1−carry) from destination |
| SETC | BIS #1,SR | Set carry bit |
| SETN | BIS #4,SR | Set negative bit |
| SETZ | BIS #2,SR | Set zero bit |
| TST.x dst | CMP.x #0,dst | Test destination |
Note that the immediate constants −1 (0xffff), 0, 1, 2, 4 and 8 can be specified in a single-word instruction without needing a separate immediate operand.
[edit]MSP430X 20-bit extension
The basic MSP430 cannot support more memory (ROM + RAM + peripherals) than its 64K address space. In order to support this, an extended form of the MSP430 uses 20-bit registers and a 20-bit address space, allowing up to 1 MB of memory. This uses the same instruction set as the basic form, but with two extensions:
- A limited number of 20-bit instructions for common operations, and
- A general prefix-word mechanism that can extend any instruction to 20 bits.
The extended instructions include some additional capabilities, notably multi-bit shifts and multi-register load/store operations.
20-bit operations use the length suffix ".A" (for address) instead of .B or .W. .W is still the default. In general, shorter operations clear the high-order bits of the destination register.
The new instructions are as follows:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Second word | Instruction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | source | 0 | 0 | opcode | destination | Extended memory-register moves | ||||||||
| 0 | 0 | 0 | 0 | src | 0 | 0 | 0 | 0 | dst | — | MOVA @Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 0 | 0 | 0 | 1 | dst | — | MOVA @Rsrc+,Rdst | ||||||
| 0 | 0 | 0 | 0 | addr[19:16] | 0 | 0 | 1 | 0 | dst | addr[15:0] | MOVA &abs20,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 0 | 0 | 1 | 1 | dst | x[15:0] | MOVA x(Rsrc),Rdst | ||||||
| 0 | 0 | 0 | 0 | n−1 | op. | 0 | 1 | 0 | W/A | destination | Bit shifts (1–4 bit positions) | ||||||
| 0 | 0 | 0 | 0 | n−1 | 0 | 0 | 0 | 1 | 0 | W/A | dst | — | RRCM.x #n,Rdst (Rotate right through carry.) | ||||
| 0 | 0 | 0 | 0 | n−1 | 0 | 1 | 0 | 1 | 0 | W/A | dst | — | RRAM.x #n,Rdst (Rotate right arithmetic, a.k.a. shift right signed.) | ||||
| 0 | 0 | 0 | 0 | n−1 | 1 | 0 | 0 | 1 | 0 | W/A | dst | — | RLAM.x #n,Rdst (Rotate left arithmetic, a.k.a. shift left.) | ||||
| 0 | 0 | 0 | 0 | n−1 | 1 | 1 | 0 | 1 | 0 | W/A | dst | — | RRUM.x #n,Rdst (Rotate right unsigned, a.k.a. shift right logical.) | ||||
| 0 | 0 | 0 | 0 | source | 0 | 1 | 1 | op. | destination | Extended register-memory moves | |||||||
| 0 | 0 | 0 | 0 | src | 0 | 1 | 1 | 0 | addr[19:16] | addr[15:0] | MOVA Rsrc,&abs20 | ||||||
| 0 | 0 | 0 | 0 | src | 0 | 1 | 1 | 1 | dst | x[15:0] | MOVA Rsrc,x(Rdst) | ||||||
| 0 | 0 | 0 | 0 | source | 1 | opcode | destination | Extended ALU operations | |||||||||
| 0 | 0 | 0 | 0 | imm[19:16] | 1 | 0 | 0 | 0 | dst | imm[15:0] | MOVA #imm20,Rdst | ||||||
| 0 | 0 | 0 | 0 | imm[19:16] | 1 | 0 | 0 | 1 | dst | imm[15:0] | CMPA #imm20,Rdst | ||||||
| 0 | 0 | 0 | 0 | imm[19:16] | 1 | 0 | 1 | 0 | dst | imm[15:0] | ADDA #imm20,Rdst | ||||||
| 0 | 0 | 0 | 0 | imm[19:16] | 1 | 0 | 1 | 1 | dst | imm[15:0] | SUBA #imm20,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 1 | 1 | 0 | 0 | dst | — | MOVA Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 1 | 1 | 0 | 1 | dst | — | CMPA Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 1 | 1 | 1 | 0 | dst | — | ADDA Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 1 | 1 | 1 | 1 | dst | — | SUBA Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | op. | mode | varies | CALLA | ||||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | RETI (Same as MSP430) |
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | As | register | CALLA source | |||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | abs[19:16] | abs[15:0] | CALLA &abs20 | |||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | x[19:16] | x[15:0] | CALLA x(PC) | |||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | — | — | (reserved) | |||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | imm[19:16] | imm[15:0] | CALLA #imm20 | |||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | — | — | (reserved) | |||||
| 0 | 0 | 0 | 1 | 0 | 1 | dir | W/A | n−1 | register | Push/pop n registers ending with specified | |||||||
| 0 | 0 | 0 | 1 | 0 | 1 | 0 | W/A | n−1 | src | — | PUSHM.x #n,Rsrc Push Rsrc, R(src−1), ... R(src−n+1) | ||||||
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | W/A | n−1 | dst−n+1 | — | POPM.x #n,Rdst Pop R(dst−n+1), R(dst−n+2), ... Rdst | ||||||
All other instructions can have a prefix word added which extends them to 20 bits. The prefix word contains an additional operand size bit, which is combined with the existing B/W bit to specify the operand size. There is one unused size combination; there are indications that this might be used in future for a 32-bit operand size.[7]
The prefix word comes in two formats, and the choice between them depends on the instruction which follows. If the instruction has any non-register operands, then the simple form is used, which provides 2 4-bit fields to extend any offset or immediate constant in the instruction stream.
If the instruction is register-to-register, a different extension word is used. This includes a "ZC" flag which suppresses carry-in (useful for instructions like DADD which always use the carry bit), and a repeat count. A 4-bit field in the extension word encodes either a repeat count (0–15 repetitions in addition to the initial execution), or a register number which contains a 4-bit repeat count.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Instruction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 | — | A/L | 0 | 0 | — | Extension word | ||||||
| 0 | 0 | 0 | 1 | 1 | src[19:16] | A/L | 0 | 0 | dst[19:16] | Memory operand extension | ||||||
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | ZC | 0 | A/L | 0 | 0 | n−1 | Register operand extension (immediate repeat count) | |||
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | ZC | 1 | A/L | 0 | 0 | Rn | Register operand extension (register repeat count) | |||
[edit]MSP430 address space
The general layout of the MSP430 address space is:
- 0x0000–0x0007
- Processor special function registers (interrupt control registers)
- 0x0008–0x00FF
- 8-bit peripherals. These must be accessed using 8-bit loads and stores.
- 0x0100–0x01FF
- 16-bit peripherals. These must be accessed using 16-bit loads and stores.
- 0x0200–0x09FF
- Up to 2048 bytes of RAM.
- 0x0C00–0x0FFF
- 1024 bytes of bootstrap loader ROM (flash parts only).
- 0x1000–0x10FF
- 256 bytes of data flash ROM (flash parts only).
- 0x1100–0x38FF
- Extended RAM on models with more than 2048 bytes of RAM. (0x1100–0x18FF is a copy of 0x0200–0x09FF)
- 0x1100–0xFFFF
- Up to 60 kilobytes of program ROM. Smaller ROMs start at higher addresses. The last 16 or 32 bytes are interrupt vectors.
A few models include more than 2048 bytes of RAM; in that case RAM begins at 0x1100. The first 2048 bytes (0x1100–0x18FF) is mirrored at 0x0200–0x09FF for compatibility. Also, some recent models bend the 8-bit and 16-bit peripheral rules, allowing 16-bit access to peripherals in the 8-bit peripheral address range.
There is a new extended version of the architecture (called MSP430X) which allows a 20-bit address space. It allows additional program ROM beginning at 0x10000.
The '5xx series has a greatly redesigned address space, with the first 4K devoted to peripherals, and up to 16K of RAM.
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